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RM0008
Figure 206. Event flags and interrupt generation
CAN_IER
Controller area network (bxCAN)
TRANSMIT
CAN_TSR
RQCP0
RQCP1
RQCP2
FMP0
+
TMEIE
FMPIE0
&
&
INTERRUPT
FIFO 0
INTERRUPT
CAN_RF0R
FULL0
FOVR0
FMP1
FFIE0
FOVIE0
FMPIE1
&
&
&
+
FIFO 1
INTERRUPT
CAN_RF1R
FULL1
FOVR1
FFIE1
FOVIE1
&
&
+
ERRIE
EWGF
EWGIE
&
CAN_ESR
EPVF
BOFF
EPVIE
BOFIE
&
&
+
ERRI
CAN_MSR
&
STATUS CHANGE
CAN_MSR
1 ? LEC ? 6
WKUI
SLAKI
LECIE
WKUIE
SLKIE
&
&
&
+
ERROR
INTERRUPT
●
The transmit interrupt can be generated by the following events:
–
–
–
Transmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set.
Transmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set.
Transmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set.
●
The FIFO 0 interrupt can be generated by the following events:
–
–
–
Reception of a new message, FMP0 bits in the CAN_RF0R register are not ‘00’.
FIFO0 full condition, FULL0 bit in the CAN_RF0R register set.
FIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set.
●
The FIFO 1 interrupt can be generated by the following events:
–
–
–
Reception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’.
FIFO1 full condition, FULL1 bit in the CAN_RF1R register set.
FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.
Doc ID 13902 Rev 9
561/995
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